# Computer Architecture

Every abstraction eventually runs on real silicon. Architecture is where
code meets voltages, gates, and clock ticks.


_Figure 001 — A ripple-carry adder: each column adds two bits and a carry, and the carry
ripples left to give the sum.
_

_Figure 002 — AND, OR, XOR — the same two inputs, three answers.
_

It begins with a switch. A transistor that is either on or off gives you a
bit, and a handful of transistors wired together give you a gate that
computes AND, OR, or NOT.


Start from that switch and build up: gates become adders, adders become a
datapath, and a datapath plus control becomes a processor that actually
executes instructions.


_Figure 003 — Overlap work to go faster.
_

The instruction set is the seam between hardware and software — a small,
fixed vocabulary the hardware implements and every compiler and program
above it is written against.


Performance is decided here. Pipelining, caches, and the memory hierarchy
explain why one loop runs ten times faster than another that looks
identical — and how to write code that uses the hardware well.


_Figure 004 — The memory hierarchy: fast & small to slow & vast.
_

Modern processors preserve a simple sequential model while executing
very differently underneath: pipelining, out-of-order execution, branch
prediction, and caches all hide latency behind that model.


_Figure 005 — A cache: a hit is instant, a miss is a trip to memory.
_

Understand the machine and you stop being surprised by it. You’ll
know why things are slow, where the limits are, and how to work
**with** the hardware instead of against it.


Everything above depends on this layer. Every language, framework, and
abstraction eventually compiles down to instructions this machine runs,
one clock tick at a time.


---

## Contents

### 1. Foundations

1. [Bits, Bytes, and Words](/computer-architecture/foundations/bits-bytes-and-words)
2. [Integer Representation](/computer-architecture/foundations/integer-representation)
3. [Integer Arithmetic](/computer-architecture/foundations/integer-arithmetic)
4. [Floating Point](/computer-architecture/foundations/floating-point)
5. [Boolean Algebra and Bit Manipulation](/computer-architecture/foundations/boolean-algebra-and-bit-manipulation)

### 2. Machine-Level Programming

1. [The Machine's View](/computer-architecture/machine-level-x86-64/the-machines-view)
2. [Data Movement](/computer-architecture/machine-level-x86-64/data-movement)
3. [Arithmetic and Logic](/computer-architecture/machine-level-x86-64/arithmetic-and-logic)
4. [Control Flow](/computer-architecture/machine-level-x86-64/control-flow)
5. [Procedures](/computer-architecture/machine-level-x86-64/procedures)
6. [Arrays, Structs, and Alignment](/computer-architecture/machine-level-x86-64/arrays-structs-and-alignment)
7. [Memory Layout and Buffer Overflows](/computer-architecture/machine-level-x86-64/memory-layout-and-buffer-overflows)

### 3. Instruction Set Architecture

1. [What an ISA Is](/computer-architecture/instruction-set-architecture/what-an-isa-is)
2. [Instruction Formats and Operands](/computer-architecture/instruction-set-architecture/instruction-formats-and-operands)
3. [Addressing Modes](/computer-architecture/instruction-set-architecture/addressing-modes)
4. [The Y86-64 Instruction Set](/computer-architecture/instruction-set-architecture/the-y86-64-instruction-set)
5. [Y86-64 Programming](/computer-architecture/instruction-set-architecture/y86-64-programming)

### 4. Digital Logic

1. [Transistors, Gates, and Boolean Functions](/computer-architecture/digital-logic/transistors-gates-and-boolean-functions)
2. [Combinational Logic and HCL](/computer-architecture/digital-logic/combinational-logic-and-hcl)
3. [Multiplexers, Decoders, and the ALU](/computer-architecture/digital-logic/multiplexers-decoders-and-the-alu)
4. [Memory Elements: Latches, Flip-Flops, and Clocking](/computer-architecture/digital-logic/memory-elements-latches-flip-flops-and-clocking)
5. [Register Files and Random-Access Memory](/computer-architecture/digital-logic/register-files-and-random-access-memory)

### 5. Processor Design

1. [The Fetch-Decode-Execute Cycle](/computer-architecture/processor-design/the-fetch-decode-execute-cycle)
2. [The SEQ Stages](/computer-architecture/processor-design/the-seq-stages)
3. [Control Logic and Sequencing](/computer-architecture/processor-design/control-logic-and-sequencing)
4. [Assembling SEQ](/computer-architecture/processor-design/assembling-seq)
5. [Tracing a Program](/computer-architecture/processor-design/tracing-a-program)

### 6. Pipelining

1. [Pipelining Principles](/computer-architecture/pipelining/pipelining-principles)
2. [From SEQ to PIPE](/computer-architecture/pipelining/from-seq-to-pipe)
3. [Data Hazards: Stalling and Forwarding](/computer-architecture/pipelining/data-hazards-stalling-and-forwarding)
4. [Control Hazards and Branch Prediction](/computer-architecture/pipelining/control-hazards-and-branch-prediction)
5. [The Complete PIPE Processor](/computer-architecture/pipelining/the-complete-pipe-processor)

### 7. The Memory Hierarchy

1. [Storage Technologies and the Latency Gap](/computer-architecture/memory-hierarchy/storage-technologies-and-the-latency-gap)
2. [Locality](/computer-architecture/memory-hierarchy/locality)
3. [Cache Memories and Direct Mapping](/computer-architecture/memory-hierarchy/cache-memories-direct-mapped)
4. [Set-Associative Caches and Write Policies](/computer-architecture/memory-hierarchy/set-associative-and-write-policies)
5. [Cache Performance and Cache-Friendly Code](/computer-architecture/memory-hierarchy/cache-performance-and-cache-friendly-code)

### 8. Virtual Memory

1. [Address Spaces and Translation](/computer-architecture/virtual-memory/address-spaces-and-translation)
2. [Page Tables and Page Faults](/computer-architecture/virtual-memory/page-tables-and-page-faults)
3. [The TLB and Multi-Level Page Tables](/computer-architecture/virtual-memory/the-tlb-and-multi-level-page-tables)

### 9. Exceptions & I/O

1. [Exceptional Control Flow](/computer-architecture/exceptions-and-io/exceptional-control-flow)
2. [Interrupts and the Kernel](/computer-architecture/exceptions-and-io/interrupts-and-the-kernel)

### 10. Multithreading & Multicore

1. [Processes, Threads, and Parallelism](/computer-architecture/multithreading-and-multicore/processes-threads-and-parallelism)
2. [Hardware Multithreading](/computer-architecture/multithreading-and-multicore/hardware-multithreading)
3. [Cache Coherence](/computer-architecture/multithreading-and-multicore/cache-coherence)
4. [Memory Consistency and Synchronization](/computer-architecture/multithreading-and-multicore/memory-consistency-and-synchronization)
5. [Multicore Organization](/computer-architecture/multithreading-and-multicore/multicore-organization)

### 11. Capstone

1. [The Whole Machine](/computer-architecture/capstone/the-whole-machine)
2. [Assembling a Complete CPU](/computer-architecture/capstone/assembling-a-complete-cpu)