---
title: RC Transients
module: Direct-Current Circuits
moduleNumber: 5
lessonNumber: 3
order: 503
summary: >
  How does a circuit get from one steady state to the next when a capacitor refuses
  to change its voltage all at once? Because a jump would demand infinite current, an
  RC circuit slides between states exponentially, with a single time constant
  $\tau=RC$ that sets the whole schedule: charging fills as $1-e^{-t/\tau}$, discharge
  empties as $e^{-t/\tau}$. We solve the first-order loop equation, read the response
  off three numbers — the switch-instant voltage, the final dc voltage, and the
  Thevenin resistance the capacitor sees — and mark where source and probe resistance
  shift $\tau$ or where a second storage element hides a mode a one-$\tau$ fit misses.
topics: [Direct-Current Circuits]
draft: false
sources:
  - book: Tipler & Mosca
    ref: "Ch. 25 — Electric Current and Direct-Current Circuits; §§25-5–25-6 Kirchhoff's Rules; RC Circuits"
---

A capacitor stores charge and electric-field energy, so its voltage is a circuit
state variable. In a finite-resistance circuit, capacitor voltage cannot change
instantaneously: a voltage jump would require an impulsive infinite current. The
initial voltage immediately after a switch changes equals the voltage immediately
before it changes. At long time in a dc circuit, capacitor current becomes zero and
the capacitor behaves as an open branch for the final-state calculation.

In a series source, resistor, and initially uncharged capacitor, Kirchhoff's loop
rule gives source emf minus resistor drop minus capacitor voltage equal to zero. With
current defined as charge rate, this is a first-order differential equation. Its
solution has charge approaching the final capacitance-times-emf value and current
decaying from the initial emf-over-resistance value. The product of resistance and
capacitance sets the time constant $\tau=RC$.

$$
% caption: Series RC charging circuit. A source of emf drives an initially uncharged capacitor C through a resistor R once the switch closes. At the instant of closure the capacitor voltage is zero and the current equals the source emf divided by R; at long time the capacitor voltage approaches the source emf and the branch current approaches zero.
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$$

The charging solution is exponential. After one time constant, capacitor voltage has
reached about sixty-three percent of its final value and current has fallen to about
thirty-seven percent of its initial value. During discharge through a resistor, the
same time constant controls exponential decay of charge, voltage, and current
magnitude. The sign of discharge current depends on the selected charging-current
reference direction.

$$
% caption: RC charging and discharge on one axis. During charging the capacitor voltage rises toward its final value as $1-e^{-t/\tau}$ (upper curve); the branch current, and equally a discharge voltage, falls toward zero as $e^{-t/\tau}$ (lower curve). One time constant $\tau=RC$ brings the charging response to about 0.63 of its final change, and by five time constants it is within one percent of final.
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$$

> **Worked example (RC charging at one time constant).** A source
> $\mathcal E=12\ \mathrm V$ charges an initially uncharged $C=3.0\ \mu\mathrm F$
> capacitor through $R=2.0\ \mathrm{M\Omega}$. Find the time constant, the final
> charge, and the charge and current at $t=\tau$.
>
> The time constant is $\tau=RC=(2.0\times10^{6})(3.0\times10^{-6})=6.0\ \mathrm s$,
> and the final charge is $q_\infty=C\mathcal E=(3.0\ \mu\mathrm F)(12\ \mathrm V)
> =36\ \mu\mathrm C$. At $t=\tau=6.0\ \mathrm s$,
>
> $$
> q=q_\infty(1-e^{-1})=36(0.632)=23\ \mu\mathrm C,
> \qquad
> i=\frac{\mathcal E}{R}e^{-1}=\frac{6.0\ \mu\mathrm A}{e}=2.2\ \mu\mathrm A.
> $$
>
> Checking the endpoints first — charge rising toward $36\ \mu\mathrm C$, current
> falling from $6.0\ \mu\mathrm A$ — catches a sign or unit slip before the
> exponential is evaluated.

## Charging equation and time-constant interpretation

An initially uncharged capacitor connected to an ideal dc source through one resistor
has charge, capacitor voltage, and current determined by the same
exponential factor. The charging solution is

$$
q(t)=C\mathcal E(1-e^{-t/(RC)}),\qquad
V_C(t)=\mathcal E(1-e^{-t/(RC)}),\qquad
i(t)=\frac{\mathcal E}{R}e^{-t/(RC)}.
$$

At zero time, capacitor voltage is zero and current has its maximum source-limited
value. At one time constant, voltage has reached about sixty-three percent of its
final value and current has fallen to about thirty-seven percent of its initial value.
At five time constants, the remaining voltage difference is less than one percent of
the final change for the ideal exponential. These reference points are practical
checks on calculator output and oscilloscope traces.

> **Worked example (voltage at two time constants).** The same network
> ($\mathcal E=12\ \mathrm V$, $R=2.0\ \mathrm{M\Omega}$, $C=3.0\ \mu\mathrm F$,
> $\tau=6.0\ \mathrm s$) is read at $t=12\ \mathrm s=2\tau$. Then
>
> $$
> V_C=\mathcal E(1-e^{-2})=12(0.865)=10.4\ \mathrm V,
> \qquad
> i=\frac{\mathcal E}{R}e^{-2}=(6.0\ \mu\mathrm A)(0.135)=0.81\ \mu\mathrm A.
> $$
>
> The voltage stays below the $12\ \mathrm V$ source and above zero throughout
> charging, as it must.

## Discharge current and polarity

When the reference current direction is selected for charging, a capacitor discharge
produces a negative calculated current. The negative sign records that the physical
current flows opposite the chosen arrow as the capacitor drives charge through the
resistor. Resistance and stored energy remain positive. Current magnitude decays as
the capacitor voltage falls, and the stored electric-field energy is converted into
thermal energy in the resistor.

Capacitor voltage is continuous through an ordinary switch event. Its value
immediately after switching equals its value immediately before switching, even when
the resistor current changes abruptly because the external circuit changes. At long
time in a dc discharge network, capacitor current approaches zero. The capacitor is
therefore treated as an open branch for the final-state circuit, while its final
voltage is set by the remaining sources and resistors. A valid transient solution
must satisfy both the initial voltage continuity and this final open-circuit state.

## Switch states, continuity, and initial conditions

Transient analysis separates the circuit into a state before switching and a state
after switching. The pre-switch circuit determines the capacitor voltage at the
instant before the event. That voltage is carried unchanged into the post-switch circuit,
where resistor currents may immediately take new values. A capacitor has stored field
energy, so its voltage is continuous; an ideal resistor stores no independent energy,
so its current can change abruptly when the surrounding connections change.

The post-switch circuit determines two quantities. Its long-time dc reduction gives
the final capacitor voltage after the capacitor branch has become open. Its terminal
resistance seen by the capacitor gives the time constant when the network is linear.
For this resistance calculation, independent ideal voltage sources are replaced by
short connections and independent ideal current sources by open branches. The
remaining resistance between capacitor terminals is the Thevenin resistance of the
post-switch network.

Initial voltage, final voltage, and terminal resistance determine the complete
first-order response. The exponential amplitude is the difference between initial and
final voltage. Its sign identifies whether the capacitor charges upward or discharges
under the selected voltage polarity. Use $V_C(0^+)$, $V_C(\infty)$, and the
post-switch Thevenin resistance to determine the response.

Endpoint checks are part of every transient calculation. A predicted voltage jump
across a finite-resistance capacitor branch or nonzero current through an ideal
capacitor after a long dc interval signals an inconsistent switch-state model.

## Differential-equation solution and sign checks

Select clockwise loop traversal and define charging current into the capacitor's
positive plate. The loop rule states that source emf is balanced by the resistor drop
and capacitor voltage. Replacing current by the rate of capacitor charge produces a
first-order equation. Rearranging separates the difference between final charge and
instantaneous charge from the time derivative. Integration gives an exponential with
the resistance-capacitance product in its denominator.

With the indicated traversal, the signed statement and its charge form are

$$
\mathcal E-iR-\frac{q}{C}=0,
\qquad i=\frac{\d q}{\d t},
\qquad
\frac{\d q}{\d t}=\frac{\mathcal E}{R}-\frac{q}{RC}.
$$

The constant term is the initial charging rate for an uncharged capacitor; the
second term is the opposing effect of charge already on the plates. Setting the rate
to zero gives the equilibrium charge $q_f=C\mathcal E$. Subtract the equilibrium
value so the remaining quantity obeys a pure decay law: the departure from final
charge is multiplied by the same exponential at every equal time interval. The
integration constant is fixed by the actual initial charge, not
by an assumed uncharged state. Thus a capacitor initially at $q_0$ has a voltage
response whose amplitude is determined by $q_0-q_f$, and the solution can be
checked at both endpoints without relying on a memorized special case.

Units offer a further safeguard: each loop term is a voltage, and the exponent must
be dimensionless, so time is compared with $RC$, never with $R/C$.

The charging current begins positive because the source drives charge onto the
selected positive plate. As capacitor voltage rises, the resistor drop decreases and
current approaches zero. The final charge makes capacitor voltage equal to source
emf, so the loop equation has zero resistor drop. These limits test the sign choice:
a charging solution that starts with negative current or exceeds final source voltage
has reversed a loop term or capacitor polarity.

For discharge with the same reference current, the resistor is driven by the
capacitor and the current is negative. Charge remains positive if the selected plate
initially holds positive charge, but its derivative is negative. The sign of current
therefore follows the derivative convention, while energy remains positive and decays
through resistor heating. Writing the reference convention beside the loop prevents
the common error of changing signs midway through a derivation.

$$
% caption: Loop-sign convention for RC charging. Traversing the loop in the current's reference direction, the source emf rises while the resistor drop $iR$ and the capacitor voltage $q/C$ fall; the current is defined as flowing onto the marked positive plate, which fixes the signs of the three terms in the first-order loop equation.
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$$

## Energy transfer and dissipation during a transient

An RC transient has a precise energy account. The electric-field energy stored in a
capacitor is $U_C=q^2/(2C)=CV_C^2/2$. During charging from an ideal source, the
instantaneous source power is $\mathcal E i$, the rate at which capacitor energy
changes is $V_Ci$, and the resistor converts $i^2R$ into thermal energy. The loop
equation $\mathcal E= iR+V_C$, multiplied by current, gives the power statement
directly: source power equals resistor heating plus the capacitor's rate of energy
increase. Each term has units of watts, providing a dimensional sign check.

Charging an initially uncharged capacitor to the emf of an ideal source requires
total source work $C\mathcal E^2$. Only half of that work remains in the
capacitor: its final field energy is $C\mathcal E^2/2$. The other half becomes
resistor heat, independent of the value of the series resistance. Resistance changes
the time scale and instantaneous current, not this ideal total. A lower resistance
delivers the same partition in a shorter time and therefore can produce a much
larger initial heating rate.

During a discharge with no source in the loop, the resistor receives the decrease in
capacitor energy. If the voltage falls from $V_i$ to $V_f$, heat deposited in the
resistor is $C(V_i^2-V_f^2)/2$. The current sign can be negative relative to a
charging arrow, but $i^2R$ remains positive: heat is generated regardless of the
chosen current reference. Resistor heating remains $i^2R\ge0$ regardless of the
current-reference direction.

The energy account must respect the circuit constraints. Charge and voltage are tied
by $q=CV_C$, and capacitor voltage is continuous through an ordinary switch event.
An ideal resistor may change its voltage and current abruptly, yet it has no stored
energy to transfer across the instant. Thus a proposed solution with a jump in
capacitor voltage implies an impulse current and lies outside the finite-resistance
model. At the beginning, during, and long after a transient, compare source work,
stored field energy, and accumulated resistor heat. Their balance exposes a missing
factor of two, a reversed source term, or an endpoint value inconsistent with the
charge constraint.

$$
% caption: Energy account for an RC transient. During charging, source work splits between energy stored in the capacitor and heat dissipated in the resistor, and for an ideal source charging from zero the two halves are equal. When the source is removed, the capacitor's stored energy flows entirely into resistor heat.
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$$

## Measurement bandwidth, loading, and data fitting

An oscilloscope or data-acquisition input loads the RC node through its resistance
and capacitance. Its input resistance adds a parallel leakage path, and its input
capacitance adds to the capacitor being measured. A probe with capacitance
$C_p$ changes an isolated capacitor $C$ to an effective capacitance close to
$C+C_p$; the resistance relevant to the time constant is the Thevenin resistance
seen at that measurement node, including the probe's input resistance when it is not
much larger. A nominal ten-megaohm probe may be harmless in a kilohm circuit but can
strongly alter a multi-megaohm timing network.

Measure the source and the capacitor node with reference leads connected to the same
intended circuit reference. A long ground lead can add inductance and ringing to a
fast edge, producing a waveform that is not described by a one-pole RC model. Check
the probe attenuation setting, input resistance, and specified capacitance before
using an observed time constant as a component result. If a second instrument is
connected, include its input path too; two apparently high-resistance meters can
combine to a significant leakage path in a high-resistance experiment.

Sampling must resolve both the early slope and the late approach to equilibrium.
Use a sample interval comfortably smaller than the expected time constant, often a
few percent of $\tau$ when noise permits, and record for several time constants so
the asymptote is visible. A record that ends near one time constant cannot reliably
separate a wrong final voltage from a wrong time constant. Conversely, a long record
with only a few points in the first tenth of a time constant poorly constrains the
initial slope and switch time.

Fit the model $V(t)=V_f+(V_i-V_f)e^{-t/\tau}$ with both endpoint voltages treated
as measured or fitted quantities when appropriate. Do not estimate $\tau$ solely
from a late, nearly flat portion of the trace: small voltage offsets then dominate.
Include data near the initial change and near the asymptote, and compare the fitted
initial and final values with independent dc measurements. Plot residuals, measured
voltage minus fitted voltage, against time. Random scatter around zero supports the
model; a systematic early bend suggests probe bandwidth or switch effects, while a
systematic late offset suggests leakage, an incorrect final voltage, or an unmodeled
parallel resistance.

$$
% caption: Probe loading at an RC measurement node. The instrument adds an input resistance $R_p$ and an input capacitance $C_p$ in parallel with the measured capacitor $C$, so the time constant seen at the node is set by the parallel combination rather than by $R$ and $C$ alone.
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$$

## Cascaded RC networks and effective time scales

Two RC stages connected in sequence do not usually behave as two independent timing
circuits. The input resistance of the second stage is a load on the first output, and
the first stage's Thevenin resistance contributes to the charging path of the second
capacitor. Writing a separate $R_1C_1$ and $R_2C_2$ product without first checking
these connections can give two time constants that belong to neither measured node.
The correct model uses Kirchhoff equations for both capacitor-node voltages, with
each capacitor current expressed as its capacitance times the corresponding voltage
derivative.

The resulting pair of first-order equations generally has two natural decay rates,
or poles. A step response at either output is therefore a weighted sum of two
exponentials rather than one exponential. If the two time scales are similar, both
terms remain visible over much of the trace and a one-pole fit will show structured
residuals. If one time scale is much longer, the faster mode fades early and the late
part of the response can be well approximated by the slow, dominant pole. That late
approximation does not establish that the complete transient had only one time
constant.

Stage isolation determines whether simple products can be used. A buffer with input
resistance far larger than the first-stage resistance and output resistance far
smaller than the second-stage resistance largely prevents the second stage from
altering the first. In that arrangement, separate one-pole descriptions become
reasonable approximations. Without a buffer, include source resistance, load resistance,
and probe input paths in the same nodal model. A high-resistance measurement probe
may still add enough capacitance to change the faster pole appreciably.

The clearest measurement diagnostic compares fits over different time windows. Fit a
single exponential to the whole record, then inspect residuals and repeat the fit
using only the late portion. A consistent late time constant with curved early
residuals indicates a hidden faster mode. Varying the load on the second stage is an
additional test: a genuine cascade changes its measured first-stage waveform when
that load changes, whereas a properly buffered first stage does not. Recording both
node voltages during the same step makes this coupling visible and helps distinguish
an actual second pole from switch delay, probe bandwidth, or random noise.

$$
% caption: Coupled two-stage RC network. The second stage draws current from the first output node, so $R_2$ and $C_2$ load the first stage; the measured response then generally contains two exponential modes rather than the single time constant of an isolated stage, unless a buffer separates them.
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$$

## Design choices: settling time, noise, and component tolerance

An RC value pair is selected from a required time scale, not from the product alone.
With fractional error $\epsilon$ remaining in a step response, the required wait
time is $t_s=-\tau\ln\epsilon$. A one-percent criterion therefore needs about
four point six time constants, while a one-tenth-percent criterion needs about six
point nine. State the error reference explicitly: a settling specification normally
means a fraction of the total voltage step, not a fraction of the instantaneous
reading. A sampled system also needs acquisition time after settling, so its cycle
time exceeds the chosen multiple of $RC$.

Many resistance-capacitance combinations have the same nominal time constant but
different physical limitations. Increasing resistance permits a smaller capacitor,
but source impedance becomes larger, input bias current and capacitor leakage cause
larger voltage errors, and a measurement probe is more likely to load the node.
Resistor thermal-voltage noise has spectral density proportional to resistance; the
RC filter shapes how much of that noise reaches the output. Increasing capacitance
can reduce sensitivity to fast interference and to sampled charge injection, but a
large real capacitor may have leakage, dielectric absorption, series resistance, and
slow recovery effects that depart from the ideal one-pole model.

Tolerance sets the spread of actual settling time. For small independent fractional
changes, $\Delta\tau/\tau$ is approximately the sum of the fractional changes in
resistance and capacitance for a worst-case bound. If tolerances are random and
independent, root-sum-square combination estimates an expected spread. A worst-case
requirement still needs its own bound. Temperature coefficients and capacitor voltage
dependence can shift the time constant after assembly even when the marked values are
accurate at room conditions. Select stable component types when timing accuracy
matters, and reserve adjustment range for the expected drift.

Calibration ties the specification to the finished circuit. Apply a known step,
measure initial and final voltage independently, and determine the time at which the
remaining difference reaches the stated error fraction. Repeat at the relevant
temperature and supply range. If the fitted time constant differs from the nominal
product, first test for source resistance, load resistance, probe capacitance, and
leakage before trimming a component. Record the nominal $RC$, tolerance budget,
settling criterion, measurement bandwidth, and calibration method.

### Switched-current sources and nonideal capacitors

An ideal current source charging an ideal capacitor produces a voltage ramp rather
than the familiar resistor-limited exponential. With current $I_0$ directed into
the selected positive plate, $I_0=C\,\d V_C/\d t$, so
$V_C(t)=V_C(0)+I_0t/C$. The slope is set by current and capacitance, while the
initial voltage remains continuous through the switch event. A practical source has
a finite compliance voltage: once the capacitor voltage approaches that limit, the
source can no longer maintain $I_0$, and the measured waveform departs from a
straight line. Switch charge injection and stray capacitance can also shift the
apparent initial condition by a small amount.

Leakage changes the long-time result even when the source remains in compliance. A
leakage resistance in parallel with the capacitor gives
$C\,\d V_C/\d t=I_0-V_C/R_{\rm leak}$. The voltage then approaches
$I_0R_{\rm leak}$ exponentially instead of increasing indefinitely. A nearly
linear early ramp followed by a gradual bend is a signature of this process.
The leak path is strongly temperature-dependent in many real capacitors, so a fit
performed at one temperature should not be assumed to predict long dwell times at
another.

Equivalent series resistance, or ESR, appears in series with the ideal capacitance.
When switched current changes abruptly, the measured terminal voltage contains an
immediate component $I\,\mathrm{ESR}$ in addition to the continuous capacitor
voltage. A terminal-voltage step can arise from ESR while charge on the ideal
capacitance remains continuous. ESR also dissipates energy and can matter in
pulsed-current tests even when its value has little effect on a slow timing interval.
Lead inductance may add ringing at a sufficiently fast switching edge, which must be
distinguished from the capacitor's intended response.

Dielectric absorption is slower and is often represented by additional small
capacitor-resistor branches. After a capacitor is charged, briefly discharged, and
left open, its terminal voltage may recover because internal polarization states
relax. The resulting tail is a sum of several exponentials, not one $RC$ curve.
To diagnose departures, record both a short, high-bandwidth trace immediately after
switching and a longer trace over the expected leakage and absorption intervals.
Fit the early slope, ESR step, and late residual separately. A systematic residual
after fitting a one-exponential model points to leakage, absorption, source
compliance, or measurement loading; it should not be hidden by quoting a single
time constant without its fit interval.

$$
% caption: Nonideal capacitor model. An equivalent series resistance (ESR) sits in series with the ideal capacitance $C$; a leakage resistance and a slow absorption branch of resistance and capacitance sit in parallel across the terminals. ESR adds an immediate step in terminal voltage, leakage bounds the long-time voltage, and the absorption branch adds slow residual tails, while the ideal capacitor voltage stays continuous at the switch instant.
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$$

## Identifying a transient model from data

A fitted exponential asserts a circuit model. The basic one-pole form is
$V(t)=V_f+(V_i-V_f)e^{-t/\tau}$, with initial voltage $V_i$, final voltage
$V_f$, and one time constant. Competing descriptions may include a switch-time
offset, a leakage path that changes $V_f$, a second exponential from a loaded or
absorbing capacitor, or a current-source ramp. These models can look similar over a
short portion of a trace. Distinguishing them requires measurements that test their
different predictions.

Measure initial and final conditions independently whenever possible. The capacitor
voltage immediately before switching fixes $V_i$ by continuity, while the
post-switch dc circuit predicts $V_f$ after sufficient time. Holding both values
fixed in a fit leaves the time constant to be inferred from the shape. If they are
allowed to float without adequate early and late data, they become correlated with
$\tau$: a slightly wrong final voltage can be compensated by a different decay
rate, producing a plausible-looking fit with a biased time constant. A record that
does not include the asymptote is especially vulnerable to this correlation.

Residuals distinguish the competing models. Subtract the fitted prediction from each
measured voltage and plot the difference against time. Random residuals centered on
zero are consistent with measurement noise and the chosen model. A prompt step in
the residual points to switch charge injection or ESR. Curvature that changes sign
over the trace often signals two time scales, while a slow one-sided tail suggests
leakage, dielectric absorption, or an incorrect final voltage. The rms residual
alone is not enough: two models may have similar rms values even when one leaves a
clear time-dependent pattern.

Use a deliberate model-selection measurement. Repeat the transient with a changed
external resistor while keeping the capacitor and instrument unchanged. A genuine
single external RC time constant should scale with that resistance after source and
load resistances are included. Then repeat with a changed capacitor or an added
known parallel leakage resistance. A second pole tied to probe capacitance or
dielectric absorption will not scale in the same way. Compare the fitted parameters
and residual structures across all runs, using the same bandwidth and synchronization
procedure. Select the simplest model that predicts the changed-run data and preserves
the independently checked endpoints; parameter count alone is not a selection
criterion.

$$
% caption: Residual test for a fitted RC model. Left, random scatter of measured minus fitted voltage about zero supports the single-exponential description; right, a systematic curved residual with an early deviation and a slow late tail reveals a missing effect such as ESR, leakage, or a second time scale.
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### Frequency response and the low-pass transfer function

The same RC network that gives an exponential step response is a frequency-selective
voltage divider. For an ideal source, a series resistor, and output taken across an
ideal capacitor, the capacitor impedance is $Z_C=1/(j\omega C)$. The complex
transfer function is therefore

$$
H(\omega)=\frac{V_{\rm out}}{V_{\rm in}}
=\frac{Z_C}{R+Z_C}=\frac{1}{1+j\omega RC}.
$$

Its magnitude and phase are $|H|=1/\sqrt{1+(\omega RC)^2}$ and
$\angle H=-\tan^{-1}(\omega RC)$. At low frequency, the capacitor impedance is
large, output nearly equals input, and phase shift is nearly zero. At high frequency,
capacitor impedance is small, output is attenuated roughly in inverse proportion to
frequency, and output approaches a ninety-degree lag. The circuit passes slowly
changing components and suppresses rapidly changing ones, hence the name low-pass.

The conventional cutoff angular frequency is $\omega_c=1/(RC)$, or
$f_c=1/(2\pi RC)$. At this point the amplitude is $1/\sqrt2$ of the low-frequency
value, corresponding to minus three decibels in power-ratio terminology, and phase
is minus forty-five degrees. Cutoff is a reference point rather than a sharp edge:
the response changes smoothly on both sides. A measured transition much sharper than
this first-order curve signals additional poles, while a different dc gain often
signals a load or source divider.

Source and load impedances belong in the transfer function. A source resistance adds
to the intended series resistance, shifting the effective time constant. A finite
load resistance in parallel with the capacitor changes both the dc output division
and the pole. In practice, replace the source-and-resistor network seen by the
capacitor with its Thevenin equivalent, then include every load path before assigning
$RC$. The ideal formula is recovered only when source resistance is included in
the stated $R$ and the output is unloaded.

A swept-sine test measures these claims without relying on a step generator. Apply a
constant, small-amplitude sine wave; record input and output amplitudes and their
relative phase at frequencies below, near, and above the expected cutoff. Keep probe
loading and source amplitude calibrated. Plot the ratio rather than output alone,
then compare the measured curve with the model using the actual source and load
resistances. A systematic phase error near cutoff often exposes channel timing or
probe effects, while a changed low-frequency ratio points to an omitted dc load.

$$
% caption: First-order RC low-pass magnitude response. The output amplitude is nearly flat well below the cutoff and rolls off smoothly above it; at the cutoff frequency $f_c=1/(2\pi RC)$ the amplitude has fallen to $1/\sqrt2\approx0.707$ of the low-frequency value, three decibels down in power.
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$$

### Connecting step response, bandwidth, and settling

The time-domain exponential and the frequency-domain transfer function describe the
same linear circuit. The impulse response of an unloaded low-pass RC network is

$$
h(t)=\frac{1}{RC}e^{-t/(RC)}
\quad\text{for }t\ge0.
$$

Convolving this response with an input waveform gives the output waveform. A unit
step integrates the impulse response and produces $1-e^{-t/(RC)}$. A sinusoidal
input samples the same response at one angular frequency and produces the complex
gain $H(\omega)$. The two descriptions agree only when the source, resistor,
capacitor, and load are represented by the same linear time-invariant model.

Bandwidth and settling specify different measurement needs. A narrow bandwidth
reduces response to fast fluctuations, while a settling requirement specifies how
long a changed dc input must be held before the remaining exponential error is small.
In a first-order step, the fraction of the final change still missing after time
$t$ is $e^{-t/\tau}$. Reaching within one percent requires about $4.6\tau$; reaching
within one tenth of one percent requires about $6.9\tau$. The ten-to-ninety percent
rise time is about $2.2\tau$. These numerical factors are tied to a stated threshold,
not to a universal definition of when a circuit has settled.

An input waveform with several frequency components can expose a limitation of a
single rise-time description. A slowly varying baseline passes through the network
with little attenuation, while a narrow pulse contains high-frequency content and
is broadened. A square wave shows both effects: its flat portions approach the dc
level, but its sharp edges round because the higher harmonics are attenuated. The
output shape depends on duty cycle, source impedance, and the interval between
transitions. Reusing a one-step settling calculation for a rapid pulse train can
produce an incorrect baseline because the capacitor has not returned to its previous
state before the next edge.

The initial-condition statement remains essential in frequency experiments. A swept
sine test starts from a transient state after each frequency change. Wait several
time constants or fit the transient and steady portions separately before estimating
amplitude and phase. A frequency response derived from data collected during
unsettled transitions can show false gain ripple or an apparent additional phase
lag. The circuit has not changed; the measurement record contains a mixture of
states.

### Component selection and a design calculation

Choose component values from the required signal bandwidth, settling interval,
source resistance, load resistance, capacitor leakage, and allowed thermal noise.

> **Worked example (sizing R and C for a settling spec).** A sensor output sampled
> after a step must settle to one percent within $0.50\ \mathrm{ms}$. Choose an
> $RC$ pair and find the cutoff frequency.
>
> One-percent settling needs $t_s=4.6\tau$, so the time constant must satisfy
>
> $$
> \tau\le\frac{t_s}{4.6}=\frac{0.50\ \mathrm{ms}}{4.6}=0.109\ \mathrm{ms}.
> $$
>
> Selecting $R=10.0\ \mathrm{k\Omega}$ and $C=10.0\ \mathrm{nF}$ gives
>
> $$
> \tau=RC=100\ \mu\mathrm s,
> \qquad
> f_c=\frac{1}{2\pi\tau}=1.59\ \mathrm{kHz},
> $$
>
> comfortably inside the $0.109\ \mathrm{ms}$ budget.

The nominal choice meets the settling requirement only if the effective resistance
seen by the capacitor is close to $10.0\ \mathrm{k\Omega}$. A $1.00\ \mathrm{k\Omega}$
source resistance increases the charging resistance to $11.0\ \mathrm{k\Omega}$,
raising the time constant by ten percent. A finite load can reduce the Thevenin
resistance and change the final dc division at the same time. Compute the Thevenin
equivalent at the capacitor terminals for each switching state before claiming that
one listed resistor is the time-setting element.

Component tolerance produces a range of time constants. A five-percent resistor and
a ten-percent capacitor can give a worst-case spread near fifteen percent when their
errors align. Temperature coefficients, dielectric bias dependence, and aging can
add a slower drift. A design close to the settling limit should reserve margin,
select tighter parts, or measure and calibrate the actual time constant. Quoting the
nominal $RC$ value alone hides whether every manufactured unit meets the timing
requirement.

$$
% caption: Tolerance envelope for a charging response. Component tolerance spreads the time constant, so the true response lies between a fast curve (low RC) and a slow curve (high RC); a sample time read from the slow curve guarantees the specified settling error across the full resistor and capacitor range.
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Noise sets a lower bound on measurement bandwidth. A resistor produces voltage noise with
mean-square value proportional to resistance, absolute temperature, and measurement
bandwidth. Reducing bandwidth lowers integrated white noise, but a slower RC response
then delays a valid reading and can distort real signal changes. Source impedance and
amplifier input current noise can add further terms. Component selection balances a
specified signal bandwidth against a specified noise floor and settling time; no
single time constant is optimal outside those stated requirements.

Capacitor technology enters the calculation. A small ceramic capacitor can have
low series resistance and compact size but a capacitance that changes with dc bias
or temperature. A film capacitor can offer stable timing at the cost of volume. An
electrolytic capacitor provides large capacitance with leakage, absorption, and
tolerance that may dominate a long time constant. Measure a representative transient
over the expected temperature and voltage range when the timing requirement is close
to the component uncertainty.

### Timing specifications and measurement protocol

A timing specification must state the threshold, initial state, final state, and
source/load connection. For a single-exponential capacitor voltage,

$$
V_C(t)=V_f+(V_i-V_f)e^{-t/\tau},
\qquad
t_{\mathrm{th}}
=-\tau\ln\!\left(\frac{V_{\mathrm{th}}-V_f}{V_i-V_f}\right),
$$

provided $V_{\mathrm{th}}$ lies between $V_i$ and $V_f$. A ten-to-ninety
percent rise time, a one-percent settling time, and a fixed comparator crossing
therefore correspond to different numerical times for one waveform. The consuming
circuit determines which definition belongs in the data sheet.

- **Threshold placement.** A threshold near $V_f$ occurs late and is sensitive to
  noise and final-value error. A threshold near $V_i$ is sensitive to switch
  delay, source-edge shape, and ESR steps. A midrange threshold gives a repeatable
  marker but does not test the late tail. Use more than one threshold, or retain the
  complete waveform, when testing the single-exponential model.
- **Time origin.** A switch command, source output edge, and voltage at the resistor
  can differ by propagation delay and finite rise time. Establish the physical start
  with a probe at the circuit input, measure the capacitor terminal with a second
  synchronized channel, and correct channel skew with a common fast edge. A low
  sample rate can interpolate a smooth exponential but cannot reconstruct an
  unobserved ESR step or short source glitch.
- **Probe model.** A nominal ten-megaohm probe in parallel with a large timing
  resistor adds leakage; its capacitance adds to the timing capacitor. An active
  probe may reduce capacitance while adding input noise and offset. Include the
  stated probe input model in the effective circuit and repeat the run with a
  second probe or buffered output whenever the estimated loading approaches the
  component tolerance.
- **Temperature and state.** Record resistor temperature, capacitor case
  temperature, supply voltage, and load state at every point. A shift following the
  known resistor or capacitor coefficient supports the component model. A shift
  appearing only after repeated switching can instead indicate self-heating,
  dielectric absorption, or source protection. Allow enough dwell time to return to
  the declared initial state.
- **Repeated triggers.** Record the full distribution of independently triggered
  crossing times. A bimodal distribution can identify switch bounce or source
  compliance transitions; a monotonic sequence can identify thermal accumulation.
  A mean and standard deviation alone conceal those signatures. Retain the trace,
  trigger definition, component state, and environmental conditions with the
  reported time constant.

> **Worked example (comparator crossing time).** A capacitor charges from
> $V_i=0$ to $V_f=5.00\ \mathrm V$, and a comparator trips at
> $V_{\mathrm{th}}=4.50\ \mathrm V$. Express the crossing time in terms of $\tau$.
>
> The threshold relation gives
>
> $$
> t_{\mathrm{th}}=-\tau\ln\!\left(\frac{V_{\mathrm{th}}-V_f}{V_i-V_f}\right)
> =-\tau\ln\!\left(\frac{4.50-5.00}{0-5.00}\right)=\tau\ln 10\approx2.30\,\tau.
> $$
>
> The same circuit spans its ten-to-ninety percent interval in $\tau\ln 9\approx
> 2.20\,\tau$, so a comparator crossing and a rise-time specification give different
> numbers for one waveform and must not be equated.

Record which threshold definition was used before fitting $\tau$. Repeating the
measurement at 10%, 50%, and 90% also tests whether one time constant describes the
entire trace or only the central portion.
Charge balance gives a final independent check on a measured transient. Integrate
the branch current through the capacitor over the interval and compare it with
$C[V_C(t_2)-V_C(t_1)]$ using the capacitance valid at the operating bias and
temperature. Agreement checks current-channel polarity, time alignment, and the
assumption that the measured current enters the modeled capacitance. A discrepancy
can expose leakage current, an unmodeled parallel branch, probe loading, or a
capacitance value that changes with voltage.

Energy provides a related check. The change in ideal capacitor energy is
$[C V_C(t_2)^2-C V_C(t_1)^2]/2$ when capacitance is constant. Compare it with the
integral of source power minus resistor and ESR heat over the same interval. A
switched circuit with a changing source or load requires every connection state in
that balance. The check cannot be reduced to the capacitor voltage trace alone,
because a voltage source may exchange charge and energy while maintaining an
apparently simple exponential endpoint.

These charge and energy tests are especially valuable after a model fit. A curve
can reproduce sampled voltages while assigning an incorrect current path or loss
mechanism. Matching the independent integrals ties the fitted time constant to the
physical capacitor, resistor, source, and measurement boundary used in the test.

In the five-volt charge example, the stored-energy change predicted by an ideal
constant capacitor is $C(5.00\ \mathrm V)^2/2$. A current integral with the
correct charge but a substantially different energy identifies a changing source
or loss path; it does not justify silently replacing the circuit by an ideal $RC$
model. Record the integration interval, the sign convention for source power, and
the resistor temperature with that comparison.